## DRV Fault GVDD

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barney
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### DRV Fault GVDD

Hi Benjamin,

i have seen your C18 workaround for GVDD fault.

It is right:
8.2.2.1 Gate Drive Average Current Load
GVDD max I = 30mA

FOC
6 x 236nC x 30kHz = 42.5mA > 30mA!

don't solder an additional C18, put the FOC frequency from 30kHz to 20kHz (28.32mA).

/Barney

benjamin
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### Re: DRV Fault GVDD

Hi Barney,

Running on 15 kHz or 20 kHz did not help. Also, the behaviour was the same when running on 40 kHz.

C18 is only 16V and GVDD is 12V, and at that voltage the capacitance probably drops below half of 2.2µF.

As far as I can tell, the 30mA limitation comes from the linear regulator from the input voltage that is used for driving the gates. Suppose that we are drawing 30mA at the specified 60V. Then the losses in the DRV are

(60 - 12) * 0.03 = 1.44w

This is quite a lot for that package, so lets suppose that this is the limit. If we use the default switching frequency of 25kHz with a fully charged 12s battery, we get 1.36w which is less than that. If 1.44w really is the reason for the 30mA limit, 25kHz should be fine. The fact that I can run on much higher switching frequency also supports this theory.

I think the problem is that when running space vector modulation, 4 or 6 switch operations can come very close to each other, which probably brings the voltage in c18 low enough to trigger the under voltage fault in the drv, especially since the capacitance only is half of the recommended value when using a 16V capacitor. Therefore adding an extra capacitor helps.

I just confirmed that I can run a motor on 70KHz with 18V input, so I don't think there is a 30mA current limit in the DRV8302.

benjamin
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### Re: DRV Fault GVDD

Some more info on this subject:

Have a look at the screenshots of gvdd xlv made in this post:
viewtopic.php?f=7&p=348&sid=a19ccde37ae8ad64af84555f60a49e06#p348

You can see that the average voltage is fine, but the switching spikes are close to 8V, which is where the DRV fault is triggered. You can also see that adding a second capacitor helps. Since the voltage recovers after the spikes, they will have the same amplitude even at lower switching frequency, meaning that you have the same problem even if you decrease fsw significantly (which is what I experienced).

In the datasheet 2.2µF is a "typical" value, not a maximum or minimum value. They also mention 200kHz and 25nC gate charge. At 200kHz and 25nC these spikes are more frequent and much smaller, which is why a smaller capacitor is enough to deal with the spikes. If fsw is decreased and the gate charge is increased, a higher value capacitor is required to take care of the spikes even if the average gate current is the same.

Another thing regarding the switching frequency: The VESC uses space vector modulation for FOC, which means that only half the amount of switching is required for a given fsw compared to "normal" modulation. During one cycle (when the vectors go from V0 to Vx to Vy to V7, or from V7 to Vy to Vx to V0 as described here https://en.wikipedia.org/wiki/Space_vector_modulation) each FET will switch either on or off, but not both on and off as with normal modulation. Therefore the current drawn from gvdd is only half of what I mentioned before, since switching the FET off does not require any extra input current.

arvidb
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### Re: DRV Fault GVDD

I've done some lame attempts to understand FOC at earlier times, but the VESC and these discussions turn out to be the best lessons ever! So a big thank you to benjamin for that!

So you have implemented some clever algorithm that makes sure that no more than one MOSFET is switched on at a time? I.e. if Vref is in the second sextant of the vector space (excuse my language, I hope that was both correct and understandable ), the sequence would be V0 to V3 to V2 to V7 and back again? (And the time at V3 and V2 would be proportional to their respective contributions to Vref - but I cannot reconcile this with the very evenly spaced switching noise in xlv's 'scope trace, so probably I've gotten this wrong...)

But if correct, it should mean that the gate charge seen by the DRV8302 would only ever be that of one MOSFET, or 236 nC. Still, a lot more than the 25 nC in the datasheet!

benjamin
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### Re: DRV Fault GVDD

I think xlv was running BLDC when he made that plot, so it would look different for FOC.

When going between two vectors, one FET is switched off and another one is switched on. Therefore you have three on-switches and three off-switches when going from V0 to V7 or when going back. One switching cycle is from V0 to V7 or from V7 to V0 (V0 and back to V0 is two cycles), so the DRV will see the load of three FETs.

arvidb
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### Re: DRV Fault GVDD

benjamin
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### Re: DRV Fault GVDD

rew
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### Re: DRV Fault GVDD

As far as I know, the firmware is "enforcing" a specific average voltage on each of the motor leads by setting a PWM value for each of the motor leads. Now classical PWM is on/off, but in this case, we're switching between "drive low" and "drive high". So each PWM cycle, both the high side and the low-side FET need to be turned on exactly once. Turning a FET ON will require power from GVDD. (but for the high-side FET, this power will be drawn from the GVDD line when the fet is turned OFF the cycle before...)

So according to my calculations the current draw from the GVDD line is: f * 6 * Qc = 25kHz * 6 fets * 236 nC / fet = 35.4mA.

As far as I can see this is six times as much as in BLDC mode: In BLDC mode you're only PWM-ing one FET at a time, correct?

Running at 12S would then easily overheat the DRV chip, although the power draw is still (but only just) below the stated 1.4W. The "max power draw" figures that you get from datasheets are always "best case" figures. To get that you have to mount the chip by its self on a really big PCB to dissipate the heat away from the chip. Of course you'll get lower numbers if you mount warm FETs near the DRV chip....

An idea might be to create a switching regulator that provides the 12V (or a little more) onto the GVDD pin. I've asked TI what they think about that idea and they replied: "hmmmm, no not supported: don't do that".

So, although I agree that the 30mA GVDD current is probably a power-limit, it is difficult to exceed the stated specs of te datasheet. For instance, the power limit would allow around 120mA at 24V input power. But with the 30mA limit in the datasheet, the linear regulator may have a current-limit circuit, tuned for anywhere from 40 to 100mA. And if they don't have a current limit now, they might "fix" an erratum in the chip (something that bothers a big client) by introducing that current limiter circuit in some revision of the chip someday....

The word from TI is: Don't use the DRV8302 for big fets like this.

solarcross
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### Re: DRV Fault GVDD

rew
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### Re: DRV Fault GVDD

No.

We (Benjamin and I) agree that we probably know /why/ TI put that spec in the datasheet. Using this knowledge allows the design to exceed a certain "absolute max" in the datasheet without expecting a bad consequence in the long run.

A simpler example is that many manufacturers specify that all pins may be a maximum of VCC+0.3V. This is due to a diode being present from each pin to VCC. That diode has a maximum current, and you're guaranteed not to exceed that current when you stay below VCC+0.3V. Great!

However, going above VCC+0.3V does not harm the diode. What harms the diode is too much current. A better spec would be "max current from pin to VCC: 1mA". Now, you can for example feed a 3.3V pin from a 12V signal, provided you keep the current below 1mA. in this case you'd calculate: Rmin = (12V-3.3V)/1mA = 8.7k. Take a little margin and you'll find that 10k or 22k works just fine. And you'll find that the voltage on the pin goes slightly higher than 3.3V + 0.3V.

At one point in time ST Microelectronics patented this trick (for BACK EMF sensing in high voltage BLDC motors). They specified that max current into the diode for a while.

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