are capacitors on mosfets between +60V and GND intentionally let out?
I copied this layout example frmo DRV8302 datasheet:
- vesc_cap_missing.png (308.38 KiB) Viewed 11584 times
Another question I have is: where on pcb is this point where signal GND and power GND is connected? Can somebody explain?
- vedder_question1.png (213 KiB) Viewed 11583 times