Ethercat for VESC

General topics and discussions about the VESC and its development.
JTAG
Posts: 11
Joined: 05 Apr 2016, 13:08
Location: Leeuwarden

Re: Ethercat for VESC

Postby JTAG » 10 Apr 2017, 21:32

By diving back into my code I found this:

Code: Select all

void ESC_write(uint16_t address, void *buf, uint16_t len) {
    volatile unsigned int int_status;
    uint16_t i;
    uint8_t *pTmpData = (uint8_t *)buf;

    /* loop for all bytes to be written */
    while ( len ) {
        if (address >= 0x1000) {
            i = len;
        }else{
            i= (len > 4) ? 4 : len;

            if(address & 01) {
               i=1;
            } else if (address & 02) {
               i= (i&1) ? 1:2;
            } else if (i == 03) {
                i=1;
            }
        }
        /* start transmission */
        PDIWriteReg(pTmpData, address, i);
        /* next address */
        len -= i;
        pTmpData += i;
        address += i;
    }
}


I should have checked this before :roll: , when "address >= 0x1000" and this is the case for sync manager 2 (SM2 @0x1100) &3 (SM3 @0x1180) it seems possible to burst write the whole struct to the fifo without the weird stuff :D (there is still some polling stuff happening in PDIWriteReg(pTmpData, address, i); but I might get around that with some tricks ). SM2 and SM3 store the PDO data, these are the only registers requiring fast updating. Once I have time ill try to implement DMA over SPI to do this! This might be an option!


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