Energy dump / overvoltage protection

Discuss hardware related to the VESC such as the NRF nunchuk.
arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Energy dump / overvoltage protection

Postby arvidb » 09 Feb 2017, 13:35

To protect the VESC and the power supply from overvoltage conditions while running "on the bench" (not powered by batteries), an energy dump circuit is needed. This has been discussed a bit in another thread but I thought it would be a good idea to create a separate thread for this topic.

rew suggested this circuit (a modification of Gecko Drive's Returned Energy Dump):
suppy_protector.png
suppy_protector.png (3.97 KiB) Viewed 1601 times


I'm at home with a cold and spent some time digging around among old components. I managed to find some power resistors (two 50 Ω ones) and a large NPN transistor (2SC3281 - note: these are obsolete since many years; if you buy one online today it's most likely a fake!). I wrote an octave script to do some calculations:
performance.png
performance.png (7.87 KiB) Viewed 1601 times

SOA_plot.png
SOA_plot.png (12.84 KiB) Viewed 1601 times


This is using a 25 Ω power resistor, the 2SC3281 transistor, a 220 Ω base resistor, and 36 V zener. (Continued in next post due to attachment limit...)

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 09 Feb 2017, 13:50

A problem with this circuit is that the base resistor power dissipation is large (almost 2.5 W at 60 V bus voltage) while there's still a lot of headroom before we violate the safe operating area of the transistor. So I added another transistor from my stash to increase the gain (this topology is apparently called a "Sziklai pair"):
Edit: This won't work, I "kindof" forgot the base resistor here. See a corrected version in a later post.
energy-dump.png
energy-dump.png (15.83 KiB) Viewed 1604 times

(As you can see I also added a series diode for additional PSU protection; this is a 6 A capable one that was also lying around in my component stash :)).

This reduces the base resistor power dissipation to about 65 mW, apparently without much change to the circuit performance. This would also let me use, say, 5 Ω power resistors, if I had them, for much better performance:
SOA_plot_Sziklai_5R.png
SOA_plot_Sziklai_5R.png (13.08 KiB) Viewed 1604 times

performance_Sziklai_5R.png
performance_Sziklai_5R.png (8.11 KiB) Viewed 1604 times
Last edited by arvidb on 09 Feb 2017, 14:01, edited 1 time in total.

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 09 Feb 2017, 13:53

Oh, and here's the octave script:

Code: Select all

Umax = 60;   # V, max bus voltage to simulate
UZ = 36;   # V, zener breakdown voltage, also simulation start
R = 25;      # Ω, value of power resistor
Rb = 8200;   # Ω, value of base resistor

# From 2SC3281 and BD440 datasheets:
hFE = 60*140; # 2SC3281 * BD440 hFE's
U_SOA = [ 0.3 10 70 200  ];
I_SOA = [20   20  2   0.1];
U_junc = 1.3 # Total junction voltage drop


U = UZ+U_junc:0.1:Umax;

Ibase = (U - UZ - U_junc) ./ Rb;
ICEmax = Ibase .* hFE;

IRmax = (U - U_junc) ./ R;

I = min(ICEmax, IRmax);

UR = I * R;
UT = U - UR;

hf = figure(1);
plot(U, I);
grid off;
title("Energy dump performance");
xlabel("Bus voltage [V]");
ylabel("Sink current [A]");

print("performance.png", "-dpng", "-S480,480");

figure(2);
loglog (UT, I, U_SOA, I_SOA);
axis([0.3 1000 0.1 50]);
set(gca, 'GridLineStyle', '-')
set(gca, 'MinorGridLineStyle', '-')
set(gca, 'XTick', [0.3 1 3 10 30 100 300 1000]);
set(gca, 'YTick', [0.1 0.3 0.5 1 3 5 10 30 50]);
# Make the numbers readable by humans:
set(gca, 'XTickLabel', num2str(get(gca, 'XTick').'))
set(gca, 'YTickLabel', num2str(get(gca, 'YTick').'))
grid on;
title("Transistor SOA plot");
xlabel("Vce [V]");
ylabel("Ic [A]");

print("SOA_plot.png", "-dpng", "-S480,480");

# Print some useful values:

disp("Peak base current [A]:")
disp(max(Ibase))
disp("Peak base resistor power dissipation [W]:")
disp(max(Ibase)^2 * Rb)

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 09 Feb 2017, 14:03

A "slightly better" (i.e., has a chance of working) version with the base resistor in the right place:
energy-dump-2.png
energy-dump-2.png (15.13 KiB) Viewed 1604 times

rew
Posts: 905
Joined: 25 Mar 2016, 12:29
Location: Delft, Netherlands.

Re: Energy dump / overvoltage protection

Postby rew » 10 Feb 2017, 09:00

Once the Q2 transistor turns on GOOD, the current into the base of the other one is unlimited. This is not good. I'd put another base resistor between the two transistors.

By using the NPN transistor construct with the zener to the powerline as I suggested, but with the current limiting resistor in the emitter instead of in the base, then you've built a voltage-controlled current source. This means that the current is quite controlled and depends on the amount of overvoltage. This should help stabilize things.

Your SOA plots worry me a bit. Apparently we can come close to the SOA line of the transistor. I don't like that. I'd like more margin. Also... with this construct, under some circumstances, the transistor gets hot, while under other conditions, the resistor is the biggest power-dump. This means two components that need cooling. If I'd need this myself, I'd try to play with the values a bit more to see if I can get "less power in the transistor". Resistors are nice components. You can easily exceed their rating by a factor of five if it is not for too long. And they don't break if they end up becoming 300C.... So I'd try and get more power into the resistor and less in the transistor.

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 10 Feb 2017, 11:37

Thanks for the feedback, rew!

rew wrote:Once the Q2 transistor turns on GOOD, the current into the base of the other one is unlimited. This is not good. I'd put another base resistor between the two transistors.

I've selected R2 so that Q2 never turns on fully. Max Q2 base current is (Umax - UZ - 0.65)/R2, or about 2.85 mA with the displayed values. BD440's hFE is 140 (typ), for a Q1 base current of 400 mA. Absolute maximum base current for Q1 is 1.5 A, so there's a bit of a margin - although the datasheet for BD440 does not list a maximum hFE, so there's that... maybe better increase R2 to 10k or 12k. Hmm, ONSemi has a vaiant (BD440G) for which they specify maximum hFE @ 500 mA to 475. That means a Q1 base current of 1.11 A with R2 = 10k, so still within limits.

Anyway, adding another base resistor between the two transistors defeats the whole purpose of this layout, which is minimizing the power dissipation of Q1's base resistor.

rew wrote:By using the NPN transistor construct with the zener to the powerline as I suggested, but with the current limiting resistor in the emitter instead of in the base, then you've built a voltage-controlled current source. This means that the current is quite controlled and depends on the amount of overvoltage. This should help stabilize things.

An interesting idea, but this fixes the voltage over the transistor so that it's equal to the zener voltage, which makes things a lot worse on the SOA plot.

rew wrote:Your SOA plots worry me a bit. Apparently we can come close to the SOA line of the transistor. I don't like that. I'd like more margin. Also... with this construct, under some circumstances, the transistor gets hot, while under other conditions, the resistor is the biggest power-dump. This means two components that need cooling. If I'd need this myself, I'd try to play with the values a bit more to see if I can get "less power in the transistor". Resistors are nice components. You can easily exceed their rating by a factor of five if it is not for too long. And they don't break if they end up becoming 300C.... So I'd try and get more power into the resistor and less in the transistor.

There's really only two ways to get better margins as far as I can tell - minimize current or voltage over the transistor, or both. Minimizing current is easy (use a larger dump resistor value) but is no fun, since it worsens the performance of the circuit. Minimizing voltage requires a fast turn-on, which also has the benefit of increasing the circuit performance. And a fast turn-on is what you get with the Darlington/Sziklai approach, right?

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 10 Feb 2017, 13:00

More funny plots... Edit: replaced the Sziklai plots with comparison plots of the original circuit (left) and the Sziklai circuit (right). (Can you tell I'm bored? :D)

These are from an improved script that better handles the pair of transistors. Before I just clumped them together as one transistor with a 1.3 V junction voltage and gain equal to the product of the individual gains (look at the former SOA_plot_Sziklai_5R.png plot: the "knee" is at 1.3 V which is a bit strange).

edump_both_performance.png
edump_both_performance.png (17.44 KiB) Viewed 1576 times

edump_both_SOA_plot.png
edump_both_SOA_plot.png (17.92 KiB) Viewed 1576 times

edump_both_comp_dissipation.png
edump_both_comp_dissipation.png (14.92 KiB) Viewed 1576 times

Peak Q1 power dissipation is about 15 W in both circuits, but the bus voltage range where Q1 dissipates the most is a lot narrower in the Sziklai circuit.

The Octave script:

Code: Select all

Umax = 60;   # V, max bus voltage to simulate
Z1 = 36;   # V, zener breakdown voltage, also simulation start
R1 = 25;   # Ω, value of power resistor
R2 = 10000;   # Ω, value of base resistor

# From 2SC3281 and BD440 datasheets:
Q1_hFE =  60; # 2SC3281
Q2_hFE = 140; # BD440
U_SOA = [ 0.3 10 70 200  ];
I_SOA = [20   20  2   0.1];
U_junc = 0.65; # Junction voltage drop


U = Z1+U_junc+0.001:0.1:Umax;

Q2_Ibase = (U - Z1 - U_junc) / R2;
Q1_Ibase = Q2_Ibase * Q2_hFE;
Q1_ICEmax = Q1_Ibase * Q1_hFE;

R1_Imax = (U - U_junc) / R1;

I = min(Q1_ICEmax, R1_Imax);
P_tot = U .* I;

R1_U = I * R1;
R1_P = R1_U .* I;
Q1_U = U - R1_U;
Q1_P = Q1_U .* I;

### Performance plot
figure(1);
ax = plotyy(U, I, U, P_tot);
xlim(ax(1), [UZ-1 Umax]);
xlim(ax(2), [UZ-1 Umax]);
grid off;
title("Energy dump performance");
xlabel("Bus voltage [V]");
ylabel(ax(1), "Sink current [A]");
ylabel(ax(2), "Total power dissipation [W]");

print("edump_performance.png", "-dpng", "-S480,480");

### Power dissipation plot
figure(2);
#ax = plotyy(U, Q1_P, U, R1_P);
#xlim(ax(1), [UZ-1 Umax]);
#xlim(ax(2), [UZ-1 Umax]);
plot(U, Q1_P, U, R1_P);
xlim([UZ-1 Umax]);
ylim([0 150]);
grid off;
title("Component power dissipation");
xlabel("Bus voltage [V]");
ylabel("Power dissipation [W]");

print("edump_comp_dissipation.png", "-dpng", "-S480,480");

### SOA plot
figure(3);
loglog (Q1_U, I, U_SOA, I_SOA);
axis([0.3 1000 0.1 50]);
set(gca, 'GridLineStyle', '-')
set(gca, 'MinorGridLineStyle', '-')
set(gca, 'XTick', [0.3 1 3 10 30 100 300 1000]);
set(gca, 'YTick', [0.1 0.3 0.5 1 3 5 10 30 50]);
# Make the numbers readable by humans:
set(gca, 'XTickLabel', num2str(get(gca, 'XTick').'))
set(gca, 'YTickLabel', num2str(get(gca, 'YTick').'))
grid on;
title("Transistor SOA plot");
xlabel("Vce [V]");
ylabel("Ic [A]");

print("edump_SOA_plot.png", "-dpng", "-S480,480");

# Print some useful values:

disp("Peak base current [A]:")
disp(max(Ibase))
disp("Peak base resistor power dissipation [W]:")
disp(max(Ibase)^2 * Rb)

rew
Posts: 905
Joined: 25 Mar 2016, 12:29
Location: Delft, Netherlands.

Re: Energy dump / overvoltage protection

Postby rew » 11 Feb 2017, 09:04

arvidb wrote:Thanks for the feedback, rew!

rew wrote:Once the Q2 transistor turns on GOOD, the current into the base of the other one is unlimited. This is not good. I'd put another base resistor between the two transistors.

I've selected R2 so that Q2 never turns on fully. Max Q2 base current is (Umax - UZ - 0.65)/R2, or about 2.85 mA with the displayed values. BD440's hFE is 140 (typ), for a Q1 base current of 400 mA. Absolute maximum base current for Q1 is 1.5 A, so there's a bit of a margin - although the datasheet for BD440 does not list a maximum hFE, so there's that... maybe better increase R2 to 10k or 12k. Hmm, ONSemi has a vaiant (BD440G) for which they specify maximum hFE @ 500 mA to 475. That means a Q1 base current of 1.11 A with R2 = 10k, so still within limits.

Anyway, adding another base resistor between the two transistors defeats the whole purpose of this layout, which is minimizing the power dissipation of Q1's base resistor.
But now you're aiming for up to 1A into the base of Q1, so now there will be 40V * 1A = 40W in the non-power-transistor Q2.
rew wrote:By using the NPN transistor construct with the zener to the powerline as I suggested, but with the current limiting resistor in the emitter instead of in the base, then you've built a voltage-controlled current source. This means that the current is quite controlled and depends on the amount of overvoltage. This should help stabilize things.

An interesting idea, but this fixes the voltage over the transistor so that it's equal to the zener voltage, which makes things a lot worse on the SOA plot.
Yes, you could also do that: no resistor in the collector of Q1. This has the advantage of a single power-element, but the disadvantage that if the power dump is large enough, you'll blow up the transistor. WITH the resistor you can limit the power to the transistor to whatever the datasheet requires.
rew wrote:Your SOA plots worry me a bit. Apparently we can come close to the SOA line of the transistor. I don't like that. I'd like more margin. Also... with this construct, under some circumstances, the transistor gets hot, while under other conditions, the resistor is the biggest power-dump. This means two components that need cooling. If I'd need this myself, I'd try to play with the values a bit more to see if I can get "less power in the transistor". Resistors are nice components. You can easily exceed their rating by a factor of five if it is not for too long. And they don't break if they end up becoming 300C.... So I'd try and get more power into the resistor and less in the transistor.

There's really only two ways to get better margins as far as I can tell - minimize current or voltage over the transistor, or both. Minimizing current is easy (use a larger dump resistor value) but is no fun, since it worsens the performance of the circuit. Minimizing voltage requires a fast turn-on, which also has the benefit of increasing the circuit performance. And a fast turn-on is what you get with the Darlington/Sziklai approach, right?


IMHO, the best thing to do would be to start with a requirement sheet. Say we want to dump 400W with a 40V nominal voltage.

Then I would decide to "stay out of it" until 45V. And have a current go up from 0A to 10A between 45V and 55V. So that means we have an emitter resistor that goes from 0 to 10A over 10V of voltage range. -> 1 Ohm. Because we want as little power in the transistor as possible, we want the transistor to be saturated at 10A. At that point there is 45V across the dump resistor. So that one is 4.5 Ohms.

For the transistor the worst case will happen at about 5A. In that case there is 50V source voltage, and 45V across Q1 and the dump. Both about half the voltage. So at that point Q1 and the load dump resistor are both dissipating about 110W.

For saturation we'll need 10A / 40 = 250mA of base-current. So Q2 needs to be something that can handle that. To prevent having to dissipate 250mA * 40V in Q2, I would put it in darlington configuration. The extra power-loss in Q1 because it can't fully saturate is not a problem here, as we're in the business of losing power. (It will be dissipating around 1.2V * max 10A = 12W at saturation while we have to cool it for 110W anyway. )

Now... if we assume that at 55V 10A is PLENTY, then we don't even need a base resistor between Q2 and the zener. that base resistor becomes necessary if we don't want to blow things up when the "client" goes above our dissipation spec..... That leaves us with finding a 43-45V zener....

So I'd get something like this:
suppy_protector.png
suppy_protector.png (4.43 KiB) Viewed 1561 times


The "TIP41" next to the transistors is not to be taken seriously. That still has to be evaluated what transistor works well...

lizardmech
Posts: 171
Joined: 19 Jan 2016, 10:54
Location: Australia

Re: Energy dump / overvoltage protection

Postby lizardmech » 11 Feb 2017, 13:26

What about using mosfets as an ideal diode? Below overvoltage levels they're on, when OV is tripped mosfets get turned off forcing current through a large power resistor. You could use it so vehicles relying on regen don't overcharge batteries, adding current sense could enable battery regen over current protection without sacrificing the ability to use braking.
Attachments
brake.png
brake.png (13.83 KiB) Viewed 1557 times

arvidb
Posts: 207
Joined: 26 Dec 2015, 14:38
Location: Sweden, Stockholm

Re: Energy dump / overvoltage protection

Postby arvidb » 11 Feb 2017, 18:15

rew wrote:But now you're aiming for up to 1A into the base of Q1, so now there will be 40V * 1A = 40W in the non-power-transistor Q2.

Heh, I woke up to that realization too. Not a good idea! Thanks for finding this bug!

rew wrote:Yes, you could also do that: no resistor in the collector of Q1. This has the advantage of a single power-element, but the disadvantage that if the power dump is large enough, you'll blow up the transistor. WITH the resistor you can limit the power to the transistor to whatever the datasheet requires.

I didn't realize that you meant add another resistor. Hmm, it works, but now there's two power resistors to handle.

Inspired by your latest circuit, I started playing with a Darlington layout. It turns out I have a bunch of BDX33C at home. I ended up with a nice and simple circuit and at the moment I cannot find anything wrong with it:
energy-dump-BDX33C.png
energy-dump-BDX33C.png (10.74 KiB) Viewed 1554 times

(BTW, the reason I'm using a 36 V zener is 1) I have one at home, and 2) I have a 35 V PSU.)


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